1. Field of the Invention
The present invention relates to the field of display, and in particular to a gate driver on array (GOA) circuit.
2. The Related Arts
The gate driver on array (GOA) technology is the array substrate column drive technology, by using the array substrate process for the LCD panel to manufacture the driver circuit for the gate scan line on the array substrate to achieve driving of the gates by line-by-line scanning.
The GOA circuit must provide the forward and backward scanning function. The common approach is to add a U2D and a D2U scanning units. For forward scanning, the forward scanning control signal U2D is high voltage, and the backward scanning control signal is low voltage. This approach requires the integrated circuit (IC) to provide the function to output the signals, which restricts the choice for the IC. Moreover, because the co-existence of U2D and D2U, the layout also imposes restrictions on the narrow border design, and a higher IC cost will incur.
Refer to FIG. 1. A known GOA circuit, applicable to low temperature polysilicon (LPTS) panel comprises: a plurality of cascade GOA units, an n-th GOA unit outputting a horizontal n-th scan signal comprising: a first thin film transistor (TFT) T1, a gate of the first TFT T1 connected to the signal output node Gn−2 of the (n−2)-th GOA unit, a source and a drain connected respectively to a node H and an input forward scan control signal U2D; a second TFT T2, a gate of the second TFT T2 connected to a node Q, a source and to drain connected respectively to the signal output node Gn and an input clock signal CKV1; a third TFT T3, a gate of the third TFT T3 connected to the signal output node Gn+2 of the (n+2)-th GOA unit, a source and adrain connected respectively to the node H and a backward scan control signal D2U; a fourth TFT T4, a gate of the fourth TFT T4 connected to a third node P, a source and a drain connected respectively to the signal output node Gn and a constant low voltage VGL; a fifth TFT T5, a gate of the fifth TFT T5 connected to a constant high voltage VGH, the source and the drain connected respectively to the first node H and the second node Q; a sixth TFT T6, a gate of the sixth TFT T6 connected to the third node P, a source and a drain connected respectively to the first node H and the constant low voltage VGL; a seventh TFT T7, a gate of the seventh TFT T7 connected to the first node H, a source and a drain connected respectively to the third node P and the constant low voltage VGL; an eighth TFT T8, a gate of the eighth TFT T8 connected to the clock signal CKV3, a source and a drain connected respectively to the third node P and the constant high voltage VGH; and a first capacitor C1, having two ends connected respectively to the second node Q and the signal output node Gn; a second capacitor C2, having two ends connected respectively to the third node P and the constant low voltage VGL. The node Q is for controlling the gate driving signal output; the node P is the stability point for maintaining the low voltage for node Q and Gn. The dash box in FIG. 1 shows the forward and backward scanning unit for the GOA circuit.
Refer to FIG. 2, which shows a schematic view of timing sequence of forward scanning in the GOA circuit of FIG. 1. Also referring to FIG. 1, the forward scanning of the circuit is described as follows:
During forward scanning, U2D is at high voltage and the D2U is at low voltage.
Stage 1, pre-charging: Gn−2 and U2D are at high voltage, T1 is conductive, node H is pre-charged, when H is at high voltage, T5 is conductive, node Q is pre-charged; when node H is at high voltage, T7 is conductive and node P is lowered down.
Stage 2, Gn outputting high voltage: in Stage 1, node Q is pre-charged and C1 maintains the charges, T2 is conductive, CKV1 outputs high voltage to Gn.
Stage 3, Gn outputting low voltage: C1 maintains the high voltage of node Q, and the low voltage of CKV1 lowers the Gn.
Stage 4, node Q lowered to VGL: when Gn+2 is at high voltage, D2U at this point is at low voltage, T3 is conductive and node Q is lowered to VGL.
Stage 5, node Q and Gn maintained at low voltage: when node Q becomes at low voltage, T7 is cut-off. When CKV3 jumps to high voltage, T8 is conductive, node P is charged to high voltage, then T4 and T6 are conductive to ensure that node Q and Gn are maintained at low voltage; at the same time, C2 maintains the node P at high voltage.
Refer to FIG. 3, which shows a schematic view of timing sequence of backward scanning in the GOA circuit of FIG. 1. Also referring to FIG. 1, the backward scanning of the circuit is described as follows:
During backward scanning, D2U is at high voltage and the U2D is at low voltage.
Stage 1, pre-charging: Gn+2 and D2U are at high voltage, T3 is conductive, node H is pre-charged; when node H is at high voltage, T5 stays in conductive state, and node Q is pre-charged; when node H is at high voltage, T7 is conductive and node P is lowered down.
Stage 2, Gn outputting high voltage: in Stage 1, node Q is pre-charged and C1 maintains the charges, T2 is conductive, CKV1 outputs high voltage to Gn.
Stage 3, Gn outputting low voltage: C1 maintains the high voltage of node Q, and the low voltage of CKV1 lowers the Gn.
Stage 4, node Q lowered to VGL: when Gn−2 is at high voltage, U2D at this point is at low voltage, T1 is conductive and node Q is lowered to VGL.
Stage 5, node Q and Gn maintained at low voltage: when node Q becomes at low voltage, T7 is cut-off. When CKV3 jumps to high voltage, T8 is conductive, node P is charged, then T4 and T6 are conductive to ensure that node Q and Gn are maintained at low voltage; at the same time, C2 keeps the node P at high voltage.